AX88796B

The AX88796B should be able to work with the standard NE2000 driver source code with some minor modifications such as the I/O base address, IRQ, CPU data accessing timing configurations. Please contact ASIX Sales (sales@asix.com.tw) to get the AX88x96B Software Programming Guide for more details.

In general, you just need to modify the I/O base address, IRQ, CPU data accessing timing of the standard NE2000 driver source code to meet the hardware requirements of your AX88796B board. You may need to modify the NE2000 driver source code to enable the following advanced features of AX88796B. Please contact ASIX Sales (sales@asix.com.tw) to get the AX88x96B Software Programming Guide for more details.
1. Flow control function
2. Wake-On-LAN function
3. VLAN function
4. Enhanced driver performance (TX Queue, Burst Read)

ASIX provides the following AX88796B drivers source codes for customers' reference. If you would like to receive these AX88796B drivers, please contact ASIX Sales (sales@asix.com.tw) directly. In the case if you need to modify the standard NE2000 driver source code to enable the advanced features of AX88796B for some other platforms, ASIX can provide the AX88796B Software Programming Guide for your reference. Please contact ASIX Sales (sales@asix.com.tw) for more details.

1. Windows CE 5.0 BSP driver and Eboot driver
2. Windows CE 4.2 BSP driver
3. Linux kernel 2.4.x/2.6.x driver and Uboot driver
4. 8051 uIP TCP/IP stack port
5. Nucleus driver
6. Vxworks driver
7. Windows XP/2000 driver

The AX88796B is a full NE2000 register level compatible Fast Ethernet controller. Below are the differences between AX88796B and NE2000,

The AX88796B supports serial EEPROM device with 16-bit data access, like 93C46 EEPROM (but not 93C56). The EEPROM device is optional for AX88796B.

The AX88796B supports both 8-bit and 16-bit CPU interfaces, like MCS-51 (805x) series, 80186 series and ISA bus. ASIX also implements AX88796B under SMDK2440 S3C2440A 32-bit ARM920T core CPU platform successfully.

No, but the AX88796 supports the MC68K CPU interface.

1. Read the Reset register (offset 1Fh) to reset MAC.
(Note: It is READ but not WRITE.)
2. Wait 1.6ms for reset completion.

The AX88796B integrates an embedded 10/100M Fast Ethernet PHY. The internal PHY address is 10h.

The AX88796B will auto-configure the MAC duplex mode to match the real duplex mode of embedded PHY so the driver doesn't need to take care about it.

The AX88796B embedded 10/100Mbps PHY/Transceiver will auto-detect a proper line speed so the driver doesn't need to take care about it.

The AX88796B supports both 8-bit and 16-bit local CPU interfaces included MCS-51 series, 80186 series and ISA bus. You shall define the proper Interrupt Trigger mode for the CPU used in bit 4 (IRQ_POL_EEP) and bit 5 (IRQ_TYPE_EEP) of EEPROM offset address 0x02. After hardware reset, AX88796B will auto-load the Interrupt Trigger mode setting from EEPROM into bit 4 and bit 5 of BTCR register. If needed, the driver can also manually set the Interrupt Trigger mode by configuring bit 4 and bit 5 of BTCR register (offset 15h) to overwrite the setting from EEPROM.

The AX88796B uses IMR register to enable/disable the interrupt function. The interrupt function can be enabled by setting a non-zero value into IMR register and can be disabled by setting a zero value into IMR register.

The AX88796B Flow Control function is disabled by default. You can enable the flow control function in full-duplex mode by setting bit 7 (Flow Control) or the back-presssure function in half-duplex mode by setting bit 6 (Back-pressure) of FCR register (offset 1Ah).

The AX88796B WOL function is disabled by default. You can enable the WOL function by configuring PMR register (Page 3, offset 0Bh) and WUCSR register (Page 3, offset 0Ah).

The AX88796B VLAN function is disabled by default. You can enable the VLAN function by setting bit 3 (VLANE) of MCR register (offset 1Bh) and configuring VIDR0 register (offset 1Ch) and VIDR1 register (offset 1Dh).

The AX88796B TX Queue and TX Buffer Ring functions are disabled by default. You can enable the TX Queue and TX Buffer Ring functions by setting bit 5 (TQCE) of MCR register (offset 1Bh) and bit 0 (TBR) of P30D register (Page3, offset 0Dh), respectively.

The AX88796B supports two kinds of Data Port for receiving/transmitting packets from/to AX88796B. One is the PIO Data Port (offset 10h); the other one is the SRAM-like Data Port (e.g. offset 800h ~ FFFh for Samsung2440 processor as described in Appendix A4 of AX88796B datasheet). The SRAM-like Data Port address range depends on which address line of host processor is being connected to the address line SA5/FIFO_SEL (pin 45) of AX88796B.

Software on host CPU can issue Single Data Read/Write command to both PIO Data Port and SRAM-like Data Port. However, to use Burst Data Read/Write commands, one has to use SRAM-like Data Port which requires SA5/FIFO_SEL (pin 45) of AX88796B connecting to an upper address line of host CPU. Our reference schematic have SA5/FIFO_SEL pin connected to upper address line for supporting Burst Data Read/Write commands.

No, but the AX88196B supports the MII interface. Please refer to AX88196B product web page for more details.

Please contact ASIX Sales (sales@asix.com.tw) directly.

You can open the gerber files of AX88796B SMDK2440 demo board by running ORACLE's AutoVue Evaluation Revision tool (30 days evaluation date). Please visit ORACLE's web site for more details.

You can open the Protel PCB layout file of AX88796B SMDK2440 demo board by running ORACLE's AutoVue Evaluation Revision tool (30 days evaluation date). Please visit ORACLE's web site for more details.